Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy. The structures and devices in the embodiments of the present disclosure are typically part of the art of single-crystal Si based material device technology.
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Therefore, methods for improving performance without scaling down dimensions have become of interest.
A proposed way to improve device performance at small dimensions is the use of double gated devices. Such a device is not simply a planar structure conducting on one surface, but conducting on two sides of the device body. A variation of the double gated device is the so called FinFET, or Tri-Gate, device. These devices are non-planar, they are three dimensional structures hosted by a fin structure. In FinFETs, the body of the transistor is formed in a fin rising out of a planar background, typically having both vertical and horizontal surfaces. The gate of the FinFET is engaging the top surface, as well as the vertically oriented body surfaces on both faces, or sidewalls, resulting in connected planes being used for transistor channel formation.